Along with improvements in the performance of information processing apparatuses such as communication backbone-oriented devices and servers, there is a desire to increase the data rates for signal transmission and reception inside and outside of the devices. For example, a greater increase in bit rate speeds is desired in the fields of high-speed input/output (I/O) and optical communications for the transmission and reception of signals within integrated circuit chips and between chips (or within devices and between devices).
A receiving circuit is expected to evaluate transferred data at a suitable timing and perform clock and data recovery (CDR). CDR is achieved by detecting the phase difference and the frequency difference between input data and a receiving (sampling) clock and then adjusting the phase of the sampling clock based on the detected information. A CDR circuit is known that does not use a reference clock even in the receiving circuit and carries out re-timing with a clock generated from the input data and then outputs data with reduced jitter.
The use of a phase detector (PD) for detecting the phase difference between the input data and a clock in a CDR circuit is well known (see, for example, Japanese Laid-open Patent Publication No. 2005-252723). The phase and the frequency of the input data and the clock are controlled so as to be matched based on the phase difference detected by the phase detector. A frequency detector (FD) that detects the frequency difference between the input data and the clock from the rotating direction of the phase is well known (see, for example, non-patent document: POTTBACKER, Ansgar et al., “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction Up to 8 Gb/s”, IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, pp. 1747-1751, December 1992).